Arrangement for correcting of seconds indication of a timepiece

ABSTRACT

A correction circuit for a timepiece is driven by digital pulses to advance the timepiece display by one second in response to each pulse. A first push button switch is provided for eliminating one pulse, and a second push button switch is provided for inserting an additional pulse into the sequence of pulses applied to the display, to thereby provide correction of the time displayed by the timepiece.

United States Patent Sauthier Jan. 22, 1974 [54] ARRANGEMENT FOR CORRECTING ()F 3,643,419 2/1972 Motta 58/23 R SECONDS INDICATION or A TIMEPIECE 3,672,155 6/1972 Betsey 3,668,859 6/1972 PolIn et al 58/85.5 X [75] Inventor: Pierre SauthIer, Bienne, Switzerland [73] Assignee: Societe Suisse Pour LIndustrie Hoflogere Mmmgement Services Pmnary ExamIner-Stephen J. Tomsky SA. Bienne Switzerland Asststant Exammer-Ed1th Simmons Jackmon Attorney, Agent, or FirmB. Franklin Griffin, Jr. et al. [22] Filed: Dec. 5, 1972 [21] Appl. No.: 312,328

' [57] ABSTRACT [30] Foreign Application Priority Data Dec. 16, 197! Great Britain 58,470/71 A correction circuit for a timepiece is driven by digital pulses to advance the timepiece display by one second [52] US. Cl. 58/23 R, 58/85.5 in response to each pulse. A first push button switch is [5 1] Int. Cl G04c 3/00 provided for eliminating one pulse, and a second push 1 Field of Search 53/23 50 button switch is provided for inserting an additional 328/44, 48; 307/222, 225 R pulse into the sequence of pulses applied to the display, to thereby provide correction of the time dis- [56] References Cited played by the timepiece.

UNITED STATES PATENTS 3,530,663 9/1970 Marti 58/23 10 Claims, 3 Drawing Figures /PJ/7Z 4/72 2/22 //)2 0 i a ARRANGEMENT FOR CORRECTING OF SECONDS INDICATION OF A TIMEPIECE BACKGROUND OF THE INVENTION The present invention concerns timepieces of the type in which a high frequency oscillating circuit stabilized for example by a quartz crystal, has its output transformed to a low' frequency through a chain of dividers and such low frequency is utilized to excite a display unit. The display unit may be in the form of a stepping motor used to drive a conventional timepiece display utilizing second, minute or hour hands, but could equally well drive a digital display formed by solid state elements or liquid crystals, or an analogue type of display likewise using solid state or liquid crystal elements.

A problem arising in timepieces of this nature is that of setting time exactly in accordance with some external time indication and one of the principal features in favor of such timepieces is the fact that they normally will be very stable and exact so that the tendency to vary from the external standard will be at aminimum over a long period of time. Normally therefore, the only resetting necessary is that of the seconds indicator since the display unit of such a timepiece is driven through a succession of pulses. It is obvious in the case, for example, of a stepping motor that in order to advance the seconds indication, it will be necessary to introduce supplemental pulses, thereby effecting additional steps of the motor. Similarily, if one wishes to retard the display it will be necessary to suppress one or more pulses driving the display unit.

A problem likely to be encountered in this respect is that of timing'Thus, for example, it is necessary that one be able to actuate the corrector at any given instant and thereby control precisely the number of seconds which one either adds to, or subtracts from, the visible display. At the same time, since we areconcerned with timepieces which should be capable of being made in wrist watch sizes, it is obvious that any arrangement provided must be simple and reliable and must keep the number of additional circuits and parts down to a minimum.

SUMMARY OF THE INVENTION An object of the present invention is to provide correction circuit means normally producing a sequence of pulses of predetermined frequency for driving a timepiece display, said correction circuit means including first means for inserting an additional pulse into said sequence of pulses, and second means for eliminating a pulse from said sequence of pulses.

A further object of the present invention is to provide a correction circuit as described in the preceding paragraph wherein said first means comprises a manually actuated switch, each actuation of which will add one pulse to said sequence, regardless of when said actuation takes place, and said second means comprises a second manually actuated switch, each actuation of which will eliminate one pulse from said sequence regardless of when said actuation takes place.

The above-stated and other objects of the invention are obtained by the provision of a timepiece in which a time standard provides signals at a predetermined frequency, said frequency being reduced through a sequence of bistable devices to a desired lower frequency and the lower frequency signals serve to control a display arrangement, and wherein means are provided to set the display exactly through the addition or subtraction of one signal at a time said means including a Reset output terminal on at least one of the bistable devices in the sequence, at least one bistable storage device arranged to be set manually and to be reset from said Reset output terminal and a display control toggle provided with two set inputs one of which receives signals from the lowest frequency one of said sequence of bistable devices and the other of which receives signals from the Set output terminal of the bistable storage device so that coincidence is prevented between signals to the motor control toggle which are manually originated and signals to the motor control toggle originating from the sequence of bistable devices.

A second bistable storage device is arranged to be set manually and reset from a Reset output terminal on the display control toggle, an output terminal of said second bistable storage device being arranged to control the conductivity of at least one transistor whereby each setting of said second bistable storage device eliminates a single signal from the sequence of display control signals.

BRIEF DESCRIPTION OF DRAWING FIG. 1 is a block diagram of the logic used for the correctors;

FIG. 2 is a timing diagram of the operation when it is desired to add pulses to the display; and,

FIG. 3 is a timing diagram of the operation when it is desired to subtract pulses from the display.

DESCRIPTION OF A PREFERRED EMBODIMENT Since the basic circuits for a timepiece of this nature may be of a known type, no attempt is made to describe them in detail. However, in general a quartz crystal controlled oscillator will have its output frequency reduced to a frequency of 1 Hz through a chain of binary counter stages. In FIG. 1 the two highest order (or lowest frequency) stages, 14 and 15, are shown. As will be obvious, when the input to stage 14 is 4 Hz, the output from stage 15 will be 1 Hz. This output is used to control the setting of a motor control bistable flip-flop CM. Resetting of such flip-flop is controlled from a stage in the binary counter chain in order to ensure synchronisation at all times. Such counter stage is chosen in a manner such that the duration of the output pulses fromflip-flop CM will be sufficient to actuate the display. In the example shown the 8th stage in the binary counter has been chosen thereby to give a duration of about 8 MS to the output pulses from CM.

A further set input to flip-flop CM is labelled S 2 and is connected to the reset output Q of a bistable storage device 16. The storage device 16 is set by means of a push-button P l and is reset from the reset output Q of the counter stage 14. As shall be subsequently explained, depression of push-button P 1 will add one pulse to the output of motor control flip-flop CM.

The output Q of flip-flop CM is connected to the base of a transistor T 2 and the collector of a transistor T l. Transistor T 2 serves to actuate the display device M which may, for example, be a standard display device actuated by a stepping motor, or one of the solid or liquid crystal display devices.

Transistor T 1 has its base connected to the output terminal Q of a bistable storage device 17. The set input of storage device 17 is actuated by a push-button P 2 and the reset input is actuated by the reset output of the motor control flip-flop CM. As will be subsequently explained depression of push-button P 2 suppresses one pulse from the output Q of flip-flop CM.

From FIG. 2 it will be noted that the output of counter stage 14 is shown as a series of pulses and the output of counter stage is shown as a further series of pulses having twice the duration of the pulses from stage 14. The output from flip-flop CM is controlled as to its duration by the reset input R and as to its timing and frequency by the set inputs S l and S 2. Thus normally S 2 will have no effect since the input thereto will remain at 1 so long as storage device 16 is not set by push-button P 1. It may be noted that the inputs S l and S 2 to flip-flop CM are in the nature of a capacitive coupled OR gate whereby an input in the form of a positive-going pulse applied to either one, will set the flip-flop. However, setting is possible only by means of a rising pulse. A steady state high level input has no effect on the flip-flop.

Thus as shown in FIG. 2, normally a pulse arrives at input S 1 from counter stage 15 each second to set flipflop CM and the flip-flop is subsequently reset at a time determined by the requirements of the display unit or, as illustrated in FIG. 1, when the 8th counter stage applies a pulse to the reset input R.

Should the user of the timepiece wish to add a second to the display indication he depresses button P 1 once, thereby providing an input to the set terminal of storage device 16. This results in providing a reset output Q from storage device 16 and subsequently will cause an additional setting of flip-flop CM thus providing an additional advance in the display unit of one second. It is of no consequence at which moment P l is depressed. At the moment of pushing button P l the output Q of the storage device 16 changes to 0. This has no effect on flip-flop CM since, as earlier explained only positive-going pulses have an effect thereon. When P 1 has been actuated, the next reset output Q from counter stage 14 returns storage device 16 to its reset condition whereby its output Q changes from O to 1. This last signal adds an additional pulse to the output from flip-flop CM. It is obvious that S 1 and S 2 cannot change from O to 1 at the same moment, in

view of the fact that the time of correction is determined by the reset output 0 from counter stage 14. Thus in FIG. 2, ti shows the instant at which a correction will be effective if P 1 has been depressed in the one-half second which precedes t As can be seen the instant t never coincides with the normal driving pulses. As shown in the example, the user may have to wait as much as one-half a second before pushing the correction button P l a second time. This difficulty may be overcome, at least in part, by the expedient of choosing the reset output from a counte stage higher up in the chain, as for instance Q 13 or Q 12 (not shown). This would reduce the waiting time necessary between the two corrections to one-fourth or one-eighth of a second. It will be evident however that this last expedient must not be pushed too far or one will risk the contrary effect. Should the push-button have any rebounding characteristic there would be a danger that where the period of reset for the storage device 16 was too short, one would risk two corrections rather than the desired one. To optimize the arrangement it may be desirable therefore to place a discriminator circuit between the push-button P l and the storage device 16.

In the case where it is desired to suppress a pulse, push-button P 2 controls bistable storage device 17. It will be evident that actuation of push-button P 2 sets storage device 17, so that Q 1. Accordingly NPN transistor T 1 becomes conductive and point B is at 0. Since point B will be at 0 between two output pulses from flip-flop CM, this would have no effect. At the moment however when the gem input signal S l arrives at flip-flop CM, the output Q changes to l and Q changes to However, point B remains at 0, since the change of Q from 1 to 0 does not change the state of storage device 17. Next following the delay, as determined by timing of the input pulse R to the flip-flop, the flip-flop CM returns to its reset state whereby QCM changes to 1. The positive-going signal Qcu resets storage device 17 (Q 0, Q l). Transistor Tl accordingly cuts off until such time as push-button P 2 has been again depressed. As will be seen from consideration of FIG. 3, one pulse and only one pulse has been eliminated. It will be seen that effectively the pushbutton P 2 will not be effective if operated at the same moment as the normal pulse being fed to the display unit. Since the duration of such a pulse however represents only about 6 percent of the duty cycle, this is thought to be of small importance. The same difficulty may arise in respect of the possible rebounding tendency of push-button P 2 as was the case of pushbutton P l and the same solution may be used to alleviate the difficulty.

I claim:

1. A correction circuit for use in a timepiece having a timing standard including a plurality of counter stages and a display means, said correction circuit comprising:

a display control flip-flop having set and reset outputs and a set input responsive to one of said counter stages for producing a sequence of signals at said set output;

circuit means responsive to each signal in said sequence of signals for energizing said display means; bistable storage means having set and reset inputs and an output;

manually operable means for applying a signal to the set input of said bistable storage means;

means for connecting the set output of said display control flip-flop to the reset input of said bistable storage means; and,

means connecting the output of said bistable storage means to said circuit means to eliminate a single signal from said sequence of signals each time said manually operable means is operated.

2. A correction circuit as claimed in claim 1 and further comprising:

second bistable storage means having set and reset inputs and an output;

second manually operable means for applying a signal to the set input of said second bistable storage means;

means connecting the output of said second bistable storage means to the set input of said display control flip-flop; and,

means responsive to one of said counter stages of higher frequency than the stage connected to the set input of said display control flip-flop for resetting said second bistable storage means.

3. A correction circuit as claimed in claim 2 wherein said display control flip-flop has a reset input connected to a counter stage of higher frequency than the stage which resets said second bistable storage means.

4. A correction circuit as claimed in claim 2 wherein the counter stages have set and reset outputs, the set input of said display control flip-flop is connected to the set output of the lowest frequency counter stage, and the reset input of said second bistable storage means is connected to the reset output of the counter stage of next higher frequency.

5. A correction circuit as claimed in claim 1 wherein said circuit means comprises a first transistor enabled by the signals of said sequency for energizing said display means.

6. A correction circuit as claimed in claim 6 wherein the means connecting the output of said bistable storage means of said circuit means includes a second transistor responsive to the output of said bistable storage means for disabling said first transistor.

7. In a timepiece wherein a time standard provides signals at a predetermined frequency and said frequency is reduced by a sequence of bistable counter stages, each having a reset output, to control a display means, the improvement comprising:

a display control flip-flop having a set input connected to one of said counter stages for producing a sequence of pulses at a set output;

means for applying said sequence of pulses to said display means;

a bistable storage means having set and reset inputs, and a set output connected to the set input of said display control flip-flop;

manually operable switch means for applying a signal to the set input of said bistable storage means; and,

means connecting the reset output of a second of said counter stages to the reset input of said bistable storage means, said second counter stage being a higher frequency stage than the counter stage connected to the set input of said display control flipflop so that coincidence is prevented between signals applied to set said display control flip-flop as a result of operating said switch means and signals applied to set said display control flip-flop as a result of operation of said one counter stage.

8. A correction circuit as claimed in claim 7 wherein said second counter stage is the next to the lowest frequency stage, and the stage connected to said display control flip-flop is the lowest frequency counter stage.

9. A correction circuit as claimed in claim 8 wherein said display control flip-flop has a reset input, and means connecting said reset input to a counter stage of a frequency greater than said next to lowest frequency stage whereby the stage selected determines the duration of each pulse in said sequence.

10. A correction circuit as claimed in claim 9 and further comprising means including a second bistable storage means for eliminating pulses from said sequence, said means comprising:

manually operable means for setting said second bistable storage means;

means connecting a reset output of said display control flip-flop to a reset input of said second bi-stable storage means; and,

means responsive to said second bistable storage means for inhibiting a single pulse from said sequence each time said manually operable means is operated. 

1. A correction circuit for use in a timepiece having a timing standard including a plurality of counter stages and a display means, said correction circuit comprising: a display control flip-flop having set and reset outputs and a set input responsive to one of said counter stages for producing a sequence of signals at said set output; circuit means responsive to each signal in said sequence of signals for energizing said display means; bistable storage means having set and reset inputs and an output; manually operable means for applying a signal to the set input of said bistable storage means; means for connecting the set output of said display control flip-flop to the reset input of said bistable storage means; and, means connecting the output of said bistable storage means to said circuit means to eliminate a single signal from said sequence of signals each time said manually operable means is operated.
 2. A correction circuit as claimed in claim 1 and further comprising: second bistable storage means having set and reset inputs and an output; second manually operable means for applying a signal to the set input of said second bistable storage means; means connecting the output of said second bistable storage means to the set input of said display control flip-flop; and, means responsive to one of said counter stages of higher frequency than the stage connected to the set input of said display control flip-flop for resetting said second bistable storage means.
 3. A correction circuit as claimed in claim 2 wherein said display control flip-flop has a reset input connected to a counter stage of higher frequency than the stage which resets said second bistable storage means.
 4. A correction circuit as claimed in claim 2 wherein the counter stages have set and reset outputs, the set input of said display control flip-flop is connected to the set output of the lowest frequency counter stage, and the reset input of said second bistable storage means is connected to the reset output of the counter stage of next higher frequency.
 5. A correction circuit as claimed in claim 1 wherein said circuit means comprises a first transistor enabled by the signals of said sequency for energizing said display means.
 6. A correction circuit as claimed in claim 6 wherein the means connecting the output of said bistable storage means of said circuit means includes a second transistor responsive to the output of said bistable storage means for disabling said first transistor.
 7. In a timepiece wherein a time standard provides signals at a predetermined frequency and said frequency is reduced by a sequence of bistable counter stages, each having a reset output, to control a display means, the improvement comprising: a display control flip-flop having a set input connected to one of said counter stages for producing a sequence of pulses at a set output; means for applying said sequence of pulses to said display means; a bistable storage means having set and reset inputs, and a set output connected to the set input of said display control flip-flop; manually operable switch means for applying a signal to the set input of said bistable storage means; and, means connecting the reset output of a second of said counter stages to the reset input of said bistable storage means, said second counter stage being a higher frequency stage than the counter stage connected to the set input of said display control flip-flop so that coincidence is prevented between signals applied to set said display control flip-flop as a result of operating said switch means and signals applied to set said display control flip-flop as a result of operation of said one counter stage.
 8. A correction circuit as claimed in claim 7 wherein said second counter stage is the next to the lowest frequency stage, and the stage connected to said display control flip-flop is the lowest frequency counter stage.
 9. A correction circuit as claimed in claim 8 wherein said display control flip-flop has a reset input, and means connecting said reset input to a counter stage of a frequency greater than said next to lowest frequency stage whereby the stage selected determines the duration of each pulse in said sequence.
 10. A correction circuit as claimed in claim 9 and further comprising means including a second bistable storage means for eliminating pulses from said sequence, said means comprising: manually operable means for setting said second bistable storage means; means connecting a reset output of said display control flip-flop to a reset input of said second bi-stable storage means; and, means responsive to said second bistable storage means for inhibiting a single pulse from said sequence each time said manually operable means is operated. 